1. Field of the Invention
This invention relates to semiconductor fabrication, and more particularly to a method for fabricating a thin film resistor over a semiconductor device.
2. Description of Related Art
In semiconductor fabrication for an integrated circuit (IC) device, the N.sup.+, P.sup.+, well and poly usually also serve as resistor layers but they have relatively lower resistance. Resistance, R, of a material typically is expressed as: EQU R={character pullout} L/A,
where {character pullout} is the resistivity of the material with a unit .OMEGA.-cm, L is the length of the material, and A is the cross-sectional area.
In order to increase resistance R, one can either reduce the cross-sectional area A or increase the length L. Since the resistor layer has its minimum cross-sectional area A in IC fabrication, one choice is increasing the length L so as to achieve the desired higher resistance R. However, as the device dimension of IC is reduced, the length L may consume too much of the available fabrication area. It is necessary to use another material with higher resistivity to take the places of N.sup.+, P.sup.+, well and poly. One of the materials with higher resistivity is SiCr, which is often used to form a thin film resistor.
FIGS. 1A-1K are cross-sectional views of a portion of a substrate, schematically illustrating conventional fabrication processes of a thin film resistor.
In FIG. 1A, a dielectric substrate 10 is provided. Below the dielectric substrate 10, several semiconductor devices formed on a semiconductor substrate may have been formed but not shown. The dielectric substrate 10 is, for example, an interconnect dielectric layer including borophosphosilicate glass (BPSG), phosphosilicate glass (PSG), Si.sub.3 N.sub.4, SiO.sub.x N.sub.y, or SiO.sub.2. The dielectric substrate 10 is formed by chemical vapor deposition (CVD).
In FIG. 1B, a thin film resistor 12 including SiCr is formed by sputtering deposition at about 300.degree. C. on the dielectric substrate 10. In FIG. 1C, a passivation layer 14 is formed on the thin film resistor 12. The passivation layer 14 including aluminum or a mix of Al/Si/Cu is used to protect the thin film resistor 12 from damages due to subsequent fabrication process. In FIG. 1D, a photoresist layer 16 with a desired pattern is formed on the passivation layer 14. In FIG. 1E, using the photoresist layer 16 as a mask, the passivation layer 14 is etched by a plasma etching process to expose a portion of the thin film resistor 12 beside the photoresist layer 16. The passivation layer 14 becomes a passivation layer 14a. The photoresist layer 16 is removed. In FIG. 1F, using the passivation layer 14a as a mask, the exposed portion of the thin film resistor 12 is removed by plasma etching. The thin film resistor 12 becomes a thin film resistor 12a.
In FIG. 1G, a metal layer 18 is formed over the dielectric substrate 10, in which the passivation layer 14a and the thin film resistor 12a are covered.
In FIG. 1H, a patterned photoresist layer 20 is formed on the metal layer 18, which has an exposed portion above the passivation layer 14a.
In FIG. 1I, using the photoresist layer 20 as a mask, a plasma etching process is performed to remove the exposed portion of the metal layer 18 so that the passivation layer 14a portion of the dielectric substrate 10 are exposed. The metal layer 18 becomes a metal layer 18a. A remaining portion of the metal layer 18 forms a metal spacer 22 on each sidewall of the passivation layer 14a and the thin film resistor 12a. The photoresist layer 20 is removed.
In FIG. 1J, a photoresist layer 24 is formed over the dielectric layer 10 is fully cover the conductive layer 18a but leave the metal spacer 22, the passivation layer 14a, and a portion of the dielectric substrate 10 at each side of the passivation layer 14a to be exposed.
In FIG. 1J and FIG. 1K, using the photoresist layer 24 as a mask, the passivation layer 14a and the metal spacer 22 are removed by wet etching so that the thin film resistor 12a is exposed. The photoresist layer 24 is removed so that there are the thin film resistor layer 12a and the metal layer 18a remaining on the dielectric substrate 10.
As an IC device is formed at a deep sub-micron level with a greatly reduced dimension, the wet etching to remove the passivation layer 14a and the metal spacer 22 of FIG. 1J in no longer suitable. Moreover, the thin film resistor 12a will be covered by a conductive layer subsequently formed over the dielectric substrate 10. It becomes difficult to change a bad thin film resistor 12a with a poor performance or to adjust the resistance of the thin film resistor 12a.
Furthermore, the conventional method for fabricating the thin film resistor 12a includes several complicate processes. The conventional method needs several plasma etching processes, which needs several times of loading/unloading on the etching machine, and several types of etchant are necessarily used. The included processes are generally not compatible with the current facility of a wafer fab so that the fabrication cost is greatly increased. In addition, the plasma remains resulting from several plasma etching process may cause a plasma damage on the IC device. The electrical properties of the IC device is degraded, resulting in a poor performance of operation.